A chalcogenide-based material, for example, has the property of being stable in either a crystalline phase or an amorphous phase at room temperature, and its resistivity changes by two to four orders of magnitude between the two phases. A nonvolatile memory is realized by making use of this property. In other words, information is written by causing a thin film of such a material to stabilize in either the crystalline or the amorphous phase, and the information is read out by detecting, through the measurement of its resistance value, whether the thin film is in the crystalline phase or the amorphous phase.
When writing information, i.e., a 1 or 0, to such a memory, the thin film of the phase-change material must undergo a phase change from crystalline to amorphous or from amorphous to crystalline. Generally, a chalcogenide-based material solidifies into the amorphous phase when the material is heated to 630° C. or higher and then cooled quickly. On the other hand, when the material is heated to 200° C. or higher and then gradually cooled it stabilizes in the crystalline phase. The thin film of the phase-change material is heated by using Joule heat that is generated when a current is passed through the thin film. When the thin film of the phase-change material has made a phase change to the amorphous phase, the resistance value of the thin film is two to four orders of magnitude larger than the resistance value the thin film would exhibit in the crystalline phase. Accordingly, by applying a read voltage to the thin film of the phase-change material and detecting the amount of current that flows, it can be determined in which phase, the amorphous phase or the crystalline phase, the thin film remains stable, and the written information can thus be read out.
Recently, it has been found that, in this kind of phase-change thin film material, the amount of current can be controlled by applying a bias voltage perpendicularly to the current flow direction. Using this property, a phase-change channel transistor having a memory function as well as a switching function has been proposed (refer to Japanese Unexamined Patent Publication No. 2005-93619). In this phase-change channel transistor, the memory function is achieved by forming the channel portion from a phase-change material, and the information read/write timing can be controlled by switching the current flowing through the channel portion on and off by the gate voltage. When a RAM is constructed using such phase-change channel transistors, each select transistor and its associated memory part can be implemented in a single transistor, and an ultra high-density storage device can be achieved. In traditional DRAM, each memory cell comprises a select transistor and a memory element formed from a capacitor, and the memory cell area increases because of the need to fabricate the capacitor on the semiconductor substrate, which has been a factor impeding device miniaturization. There has therefore been a limit to the extent to which memory cell density can be increased.
Since there has been a limit to the miniaturization of the memory cell, a multi-value recording method has been proposed that writes multi-value information to each device to achieve a further increase in recording density (for example, refer to WO 2005/031725 and Japanese Unexamined Patent Publication No. 2006-155700). When writing and reading binary information to and from a phase-change memory device, a 0 or 1 is written by causing the entire memory layer, for example, to change phase to a crystalline phase or an amorphous phase, respectively, and the thus written 0 or 1 is read out by detecting the resistance value of the memory layer held in that state. To achieve a multi-value recording, the memory layer must be made to exhibit a resistance value intermediate between the value it exhibits when the entire memory layer is in the crystalline phase and the value it exhibits when it is in the amorphous phase, by controlling the grain size of the crystalline phase, the change in the ratio of its volume, and the change in the volume of the amorphous phase that occur when the memory layer undergoes a phase change.
FIG. 1 is a diagram explaining a prior art multi-value recording method for a phase-change memory. FIG. 1(a) shows a state in which a 0 is recorded by causing the entire area of memory layer 2 to change to the crystalline phase (c ). FIG. 1(b) shows a state in which a 1 is written by causing, for example, one-quarter of the entire area of memory layer 2 to change to the amorphous (α) phase. FIG. 1(c) shows a state in which a 2 is written by causing, for example, one-half of the entire area of memory layer 2 to change to the amorphous phase. Further, FIG. 1(d) shows a state in which a 3 is written by causing the entire area of memory layer 2 to change to the amorphous phase.
When memory layer 2 is partially amorphized in a step-like manner as shown in parts (a) to (d) of FIG. 1, its resistance value changes in a step-like manner between the low resistance value associated with the crystalline phase and the high resistance value associated with the amorphous phase, and thus written information ranging from a 0 to a 3 can be read out by reading the resistance value of the memory layer 2. Theoretically, further multi-valued information can be recorded by partially amorphizing the memory layer 2 in finer steps. It will be appreciated here that the intermediate values can also be written and read out if a 0 is written by setting the entire memory layer 2 in the amorphous phase and a 1 written by setting it in the crystalline phase.
To cause the memory layer 2 to change to each of the (a) to (d) states, the temperature of the memory layer 2 must be controlled by controlling the number of write pulses. For example, one write pulse is applied to the memory layer 2 in the crystalline state to amorphizing a portion of the memory layer to write a 1, two write pulses are applied to write a 2, and three write pulses are applied to write a 3.
FIG. 2 shows the structure of a phase-change memory device capable of multi-value recording such as described above. Part (a) of FIG. 2 is a plan view of the phase-change memory device 4, and part (b) is a cross-sectional view taken along line A-A in part (a). In parts (a) and (b) of FIG. 2, reference numeral 6 is a semiconductor substrate of Si or the like, 8 is an insulating film of SiO2 or the like formed on the semiconductor substrate 6, and 10 and 12 are first and second electrode layers formed on the insulating film 8. A memory layer 2 formed from a phase-change material such as chalcogenide is deposited on the insulating film 8 exposed between the first and second electrode layers 10 and 12 by using, for example, a plasma CVD method or the like.
The prior art multi-value recording phase-change memory device achieves multi-value recording by utilizing the change in the volume ratio between the crystalline phase area and the amorphous phase area in the memory layer 2, as earlier described. However, since this volume ratio changes with the size of the memory layer, the number of phase changes, etc., the volume of the amorphized area varies appreciably even when the same write pulse is applied. Accordingly, if the margin for the resistance value is small when recording a 0, a 1, a 2, a 3, etc., multi-value recording becomes difficult to achieve.